Ubunt信息如下。
root@hanyw:~# cat /etc/os-release
PRETTY_NAME="Ubuntu 22.04.1 LTS"
NAME="Ubuntu"
VERSION_ID="22.04"
VERSION="22.04.1 LTS (Jammy Jellyfish)"
VERSION_CODENAME=jammy
ID=ubuntu
ID_LIKE=debian
HOME_URL="https://www.ubuntu.com/"
SUPPORT_URL="https://help.ubuntu.com/"
BUG_REPORT_URL="https://bugs.launchpad.net/ubuntu/"
PRIVACY_POLICY_URL="https://www.ubuntu.com/legal/terms-and-policies/privacy-policy"
UBUNTU_CODENAME=jammy
GCC信息如下。
root@hanyw:~# gcc --version
gcc (Ubuntu 11.3.0-1ubuntu1~22.04) 11.3.0
Copyright (C) 2021 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
GCC帮助手册的第16小节，第10288~11288行，如下。
10288 Most extension names are generically named, but have an effect that is dependent upon the architecture to
10289 which it is applied. For example, the simd option can be applied to both armv7-a and armv8-a
10290 architectures, but will enable the original ARMv7-A Advanced SIMD (Neon) extensions for armv7-a and the
10291 ARMv8-A variant for armv8-a.
10292 The table below lists the supported extensions for each architecture. Architectures not mentioned do not
10293 support any extensions.
10294 armv5te
10295 armv6
10296 armv6j
10297 armv6k
10298 armv6kz
10299 armv6t2
10300 armv6z
10301 armv6zk
10302 fp The VFPv2 floating-point instructions. The extension vfpv2 can be used as an alias for this
10303 extension.
10304 nofp
10305 Disable the floating-point instructions.
10306 armv7
10307 The common subset of the ARMv7-A, ARMv7-R and ARMv7-M architectures.
10308 fp The VFPv3 floating-point instructions, with 16 double-precision registers. The extension
10309 vfpv3-d16 can be used as an alias for this extension. Note that floating-point is not supported
10310 by the base ARMv7-M architecture, but is compatible with both the ARMv7-A and ARMv7-R
10311 architectures.
10312 nofp
10313 Disable the floating-point instructions.
10314 armv7-a
10315 mp The multiprocessing extension.
10316 sec
10317 The security extension.
10318 fp The VFPv3 floating-point instructions, with 16 double-precision registers. The extension
10319 vfpv3-d16 can be used as an alias for this extension.
10320 simd
10321 The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions. The extensions neon and
10322 neon-vfpv3 can be used as aliases for this extension.
10323 vfpv3
10324 The VFPv3 floating-point instructions, with 32 double-precision registers.
10325 vfpv3-d16-fp16
10326 The VFPv3 floating-point instructions, with 16 double-precision registers and the half-precision
10327 floating-point conversion operations.
10328 vfpv3-fp16
10329 The VFPv3 floating-point instructions, with 32 double-precision registers and the half-precision
10330 floating-point conversion operations.
10331 vfpv4-d16
10332 The VFPv4 floating-point instructions, with 16 double-precision registers.
10333 vfpv4
10334 The VFPv4 floating-point instructions, with 32 double-precision registers.
10335 neon-fp16
10336 The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions, with the half-precision
10337 floating-point conversion operations.
10338 neon-vfpv4
10339 The Advanced SIMD (Neon) v2 and the VFPv4 floating-point instructions.
10340 nosimd
10341 Disable the Advanced SIMD instructions (does not disable floating point).
10342 nofp
10343 Disable the floating-point and Advanced SIMD instructions.
10344 armv7ve
10345 The extended version of the ARMv7-A architecture with support for virtualization.
10346 fp The VFPv4 floating-point instructions, with 16 double-precision registers. The extension
10347 vfpv4-d16 can be used as an alias for this extension.
10348 simd
10349 The Advanced SIMD (Neon) v2 and the VFPv4 floating-point instructions. The extension neon-vfpv4
10350 can be used as an alias for this extension.
10351 vfpv3-d16
10352 The VFPv3 floating-point instructions, with 16 double-precision registers.
10353 vfpv3
10354 The VFPv3 floating-point instructions, with 32 double-precision registers.
10355 vfpv3-d16-fp16
10356 The VFPv3 floating-point instructions, with 16 double-precision registers and the half-precision
10357 floating-point conversion operations.
10358 vfpv3-fp16
10359 The VFPv3 floating-point instructions, with 32 double-precision registers and the half-precision
10360 floating-point conversion operations.
10361 vfpv4-d16
10362 The VFPv4 floating-point instructions, with 16 double-precision registers.
10363 vfpv4
10364 The VFPv4 floating-point instructions, with 32 double-precision registers.
10365 neon
10366 The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions. The extension neon-vfpv3
10367 can be used as an alias for this extension.
10368 neon-fp16
10369 The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions, with the half-precision
10370 floating-point conversion operations.
10371 nosimd
10372 Disable the Advanced SIMD instructions (does not disable floating point).
10373 nofp
10374 Disable the floating-point and Advanced SIMD instructions.
10375 armv8-a
10376 crc
10377 The Cyclic Redundancy Check (CRC) instructions.
10378 simd
10379 The ARMv8-A Advanced SIMD and floating-point instructions.
10380 crypto
10381 The cryptographic instructions.
10382 nocrypto
10383 Disable the cryptographic instructions.
10384 nofp
10385 Disable the floating-point, Advanced SIMD and cryptographic instructions.
10386 sb Speculation Barrier Instruction.
10387 predres
10388 Execution and Data Prediction Restriction Instructions.
10389 armv8.1-a
10390 simd
10391 The ARMv8.1-A Advanced SIMD and floating-point instructions.
10392 crypto
10393 The cryptographic instructions. This also enables the Advanced SIMD and floating-point
10394 instructions.
10395 nocrypto
10396 Disable the cryptographic instructions.
10397 nofp
10398 Disable the floating-point, Advanced SIMD and cryptographic instructions.
10399 sb Speculation Barrier Instruction.
10400 predres
10401 Execution and Data Prediction Restriction Instructions.
10402 armv8.2-a
10403 armv8.3-a
10404 fp16
10405 The half-precision floating-point data processing instructions. This also enables the Advanced
10406 SIMD and floating-point instructions.
10407 fp16fml
10408 The half-precision floating-point fmla extension. This also enables the half-precision floating-
10409 point extension and Advanced SIMD and floating-point instructions.
10410 simd
10411 The ARMv8.1-A Advanced SIMD and floating-point instructions.
10412 crypto
10413 The cryptographic instructions. This also enables the Advanced SIMD and floating-point
10414 instructions.
10415 dotprod
10416 Enable the Dot Product extension. This also enables Advanced SIMD instructions.
10417 nocrypto
10418 Disable the cryptographic extension.
10419 nofp
10420 Disable the floating-point, Advanced SIMD and cryptographic instructions.
10421 sb Speculation Barrier Instruction.
10422 predres
10423 Execution and Data Prediction Restriction Instructions.
10424 i8mm
10425 8-bit Integer Matrix Multiply instructions. This also enables Advanced SIMD and floating-point
10426 instructions.
10427 bf16
10428 Brain half-precision floating-point instructions. This also enables Advanced SIMD and floating-
10429 point instructions.
10430 armv8.4-a
10431 fp16
10432 The half-precision floating-point data processing instructions. This also enables the Advanced
10433 SIMD and floating-point instructions as well as the Dot Product extension and the half-precision
10434 floating-point fmla extension.
10435 simd
10436 The ARMv8.3-A Advanced SIMD and floating-point instructions as well as the Dot Product extension.
10437 crypto
10438 The cryptographic instructions. This also enables the Advanced SIMD and floating-point
10439 instructions as well as the Dot Product extension.
10440 nocrypto
10441 Disable the cryptographic extension.
10442 nofp
10443 Disable the floating-point, Advanced SIMD and cryptographic instructions.
10444 sb Speculation Barrier Instruction.
10445 predres
10446 Execution and Data Prediction Restriction Instructions.
10447 i8mm
10448 8-bit Integer Matrix Multiply instructions. This also enables Advanced SIMD and floating-point
10449 instructions.
10450 bf16
10451 Brain half-precision floating-point instructions. This also enables Advanced SIMD and floating-
10452 point instructions.
10453 armv8.5-a
10454 fp16
10455 The half-precision floating-point data processing instructions. This also enables the Advanced
10456 SIMD and floating-point instructions as well as the Dot Product extension and the half-precision
10457 floating-point fmla extension.
10458 simd
10459 The ARMv8.3-A Advanced SIMD and floating-point instructions as well as the Dot Product extension.
10460 crypto
10461 The cryptographic instructions. This also enables the Advanced SIMD and floating-point
10462 instructions as well as the Dot Product extension.
10463 nocrypto
10464 Disable the cryptographic extension.
10465 nofp
10466 Disable the floating-point, Advanced SIMD and cryptographic instructions.
10467 i8mm
10468 8-bit Integer Matrix Multiply instructions. This also enables Advanced SIMD and floating-point
10469 instructions.
10470 bf16
10471 Brain half-precision floating-point instructions. This also enables Advanced SIMD and floating-
10472 point instructions.
10473 armv8.6-a
10474 fp16
10475 The half-precision floating-point data processing instructions. This also enables the Advanced
10476 SIMD and floating-point instructions as well as the Dot Product extension and the half-precision
10477 floating-point fmla extension.
10478 simd
10479 The ARMv8.3-A Advanced SIMD and floating-point instructions as well as the Dot Product extension.
10480 crypto
10481 The cryptographic instructions. This also enables the Advanced SIMD and floating-point
10482 instructions as well as the Dot Product extension.
10483 nocrypto
10484 Disable the cryptographic extension.
10485 nofp
10486 Disable the floating-point, Advanced SIMD and cryptographic instructions.
10487 i8mm
10488 8-bit Integer Matrix Multiply instructions. This also enables Advanced SIMD and floating-point
10489 instructions.
10490 bf16
10491 Brain half-precision floating-point instructions. This also enables Advanced SIMD and floating-
10492 point instructions.
10493 armv7-r
10494 fp.sp
10495 The single-precision VFPv3 floating-point instructions. The extension vfpv3xd can be used as an
10496 alias for this extension.
10497 fp The VFPv3 floating-point instructions with 16 double-precision registers. The extension vfpv3-d16
10498 can be used as an alias for this extension.
10499 vfpv3xd-d16-fp16
10500 The single-precision VFPv3 floating-point instructions with 16 double-precision registers and the
10501 half-precision floating-point conversion operations.
10502 vfpv3-d16-fp16
10503 The VFPv3 floating-point instructions with 16 double-precision registers and the half-precision
10504 floating-point conversion operations.
10505 nofp
10506 Disable the floating-point extension.
10507 idiv
10508 The ARM-state integer division instructions.
10509 noidiv
10510 Disable the ARM-state integer division extension.
10511 armv7e-m
10512 fp The single-precision VFPv4 floating-point instructions.
10513 fpv5
10514 The single-precision FPv5 floating-point instructions.
10515 fp.dp
10516 The single- and double-precision FPv5 floating-point instructions.
10517 nofp
10518 Disable the floating-point extensions.
10519 armv8.1-m.main
10520 dsp
10521 The DSP instructions.
10522 mve
10523 The M-Profile Vector Extension (MVE) integer instructions.
10524 mve.fp
10525 The M-Profile Vector Extension (MVE) integer and single precision floating-point instructions.
10526 fp The single-precision floating-point instructions.
10527 fp.dp
10528 The single- and double-precision floating-point instructions.
10529 nofp
10530 Disable the floating-point extension.
10531 cdecp0, cdecp1, ... , cdecp7
10532 Enable the Custom Datapath Extension (CDE) on selected coprocessors according to the numbers given
10533 in the options in the range 0 to 7.
10534 armv8-m.main
10535 dsp
10536 The DSP instructions.
10537 nodsp
10538 Disable the DSP extension.
10539 fp The single-precision floating-point instructions.
10540 fp.dp
10541 The single- and double-precision floating-point instructions.
10542 nofp
10543 Disable the floating-point extension.
10544 cdecp0, cdecp1, ... , cdecp7
10545 Enable the Custom Datapath Extension (CDE) on selected coprocessors according to the numbers given
10546 in the options in the range 0 to 7.
10547 armv8-r
10548 crc
10549 The Cyclic Redundancy Check (CRC) instructions.
10550 fp.sp
10551 The single-precision FPv5 floating-point instructions.
10552 simd
10553 The ARMv8-A Advanced SIMD and floating-point instructions.
10554 crypto
10555 The cryptographic instructions.
10556 nocrypto
10557 Disable the cryptographic instructions.
10558 nofp
10559 Disable the floating-point, Advanced SIMD and cryptographic instructions.
10560 -march=native causes the compiler to auto-detect the architecture of the build computer. At present, this
10561 feature is only supported on GNU/Linux, and not all architectures are recognized. If the auto-detect is
10562 unsuccessful the option has no effect.
10563 -mtune=name
10564 This option specifies the name of the target ARM processor for which GCC should tune the performance of the
10565 code. For some ARM implementations better performance can be obtained by using this option. Permissible
10566 names are: arm7tdmi, arm7tdmi-s, arm710t, arm720t, arm740t, strongarm, strongarm110, strongarm1100,
10567 0strongarm1110, arm8, arm810, arm9, arm9e, arm920, arm920t, arm922t, arm946e-s, arm966e-s, arm968e-s,
10568 arm926ej-s, arm940t, arm9tdmi, arm10tdmi, arm1020t, arm1026ej-s, arm10e, arm1020e, arm1022e, arm1136j-s,
10569 arm1136jf-s, mpcore, mpcorenovfp, arm1156t2-s, arm1156t2f-s, arm1176jz-s, arm1176jzf-s, generic-armv7-a,
10570 cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, cortex-a17, cortex-a32, cortex-a35,
10571 cortex-a53, cortex-a55, cortex-a57, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae,
10572 cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, ares, cortex-r4, cortex-r4f, cortex-r5, cortex-r7,
10573 cortex-r8, cortex-r52, cortex-m0, cortex-m0plus, cortex-m1, cortex-m3, cortex-m4, cortex-m7, cortex-m23,
10574 cortex-m33, cortex-m35p, cortex-m55, cortex-x1, cortex-m1.small-multiply, cortex-m0.small-multiply,
10575 cortex-m0plus.small-multiply, exynos-m1, marvell-pj4, neoverse-n1, neoverse-n2, neoverse-v1, xscale,
10576 iwmmxt, iwmmxt2, ep9312, fa526, fa626, fa606te, fa626te, fmp626, fa726te, xgene1.
10577 Additionally, this option can specify that GCC should tune the performance of the code for a big.LITTLE
10578 system. Permissible names are: cortex-a15.cortex-a7, cortex-a17.cortex-a7, cortex-a57.cortex-a53,
10579 cortex-a72.cortex-a53, cortex-a72.cortex-a35, cortex-a73.cortex-a53, cortex-a75.cortex-a55,
10580 cortex-a76.cortex-a55.
10581 -mtune=generic-arch specifies that GCC should tune the performance for a blend of processors within
10582 architecture arch. The aim is to generate code that run well on the current most popular processors,
10583 balancing between optimizations that benefit some CPUs in the range, and avoiding performance pitfalls of
10584 other CPUs. The effects of this option may change in future GCC versions as CPU models come and go.
10585 -mtune permits the same extension options as -mcpu, but the extension options do not affect the tuning of
10586 the generated code.
10587 -mtune=native causes the compiler to auto-detect the CPU of the build computer. At present, this feature
10588 is only supported on GNU/Linux, and not all architectures are recognized. If the auto-detect is
10589 unsuccessful the option has no effect.
10590 -mcpu=name[ extension...]
10591 This specifies the name of the target ARM processor. GCC uses this name to derive the name of the target
10592 ARM architecture (as if specified by -march) and the ARM processor type for which to tune for performance
10593 (as if specified by -mtune). Where this option is used in conjunction with -march or -mtune, those options
10594 take precedence over the appropriate part of this option.
10595 Many of the supported CPUs implement optional architectural extensions. Where this is so the architectural
10596 extensions are normally enabled by default. If implementations that lack the extension exist, then the
10597 extension syntax can be used to disable those extensions that have been omitted. For floating-point and
10598 Advanced SIMD (Neon) instructions, the settings of the options -mfloat-abi and -mfpu must also be
10599 considered: floating-point and Advanced SIMD instructions will only be used if -mfloat-abi is not set to
10600 soft; and any setting of -mfpu other than auto will override the available floating-point and SIMD
10601 extension instructions.
10602 For example, cortex-a9 can be found in three major configurations: integer only, with just a floating-point
10603 unit or with floating-point and Advanced SIMD. The default is to enable all the instructions, but the
10604 extensions nosimd and nofp can be used to disable just the SIMD or both the SIMD and floating-point
10605 instructions respectively.
10606 Permissible names for this option are the same as those for -mtune.
10607 The following extension options are common to the listed CPUs:
10608 nodsp
10609 Disable the DSP instructions on cortex-m33, cortex-m35p.
10610 nofp
10611 Disables the floating-point instructions on arm9e, arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e,
10612 arm1022e, arm926ej-s, arm1026ej-s, cortex-r5, cortex-r7, cortex-r8, cortex-m4, cortex-m7, cortex-m33
10613 and cortex-m35p. Disables the floating-point and SIMD instructions on generic-armv7-a, cortex-a5,
10614 cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, cortex-a17, cortex-a15.cortex-a7,
10615 cortex-a17.cortex-a7, cortex-a32, cortex-a35, cortex-a53 and cortex-a55.
10616 nofp.dp
10617 Disables the double-precision component of the floating-point instructions on cortex-r5, cortex-r7,
10618 cortex-r8, cortex-r52 and cortex-m7.
10619 nosimd
10620 Disables the SIMD (but not floating-point) instructions on generic-armv7-a, cortex-a5, cortex-a7 and
10621 cortex-a9.
10622 crypto
10623 Enables the cryptographic instructions on cortex-a32, cortex-a35, cortex-a53, cortex-a55, cortex-a57,
10624 cortex-a72, cortex-a73, cortex-a75, exynos-m1, xgene1, cortex-a57.cortex-a53, cortex-a72.cortex-a53,
10625 cortex-a73.cortex-a35, cortex-a73.cortex-a53 and cortex-a75.cortex-a55.
10626 Additionally the generic-armv7-a pseudo target defaults to VFPv3 with 16 double-precision registers. It
10627 supports the following extension options: mp, sec, vfpv3-d16, vfpv3, vfpv3-d16-fp16, vfpv3-fp16, vfpv4-d16,
10628 vfpv4, neon, neon-vfpv3, neon-fp16, neon-vfpv4. The meanings are the same as for the extensions to
10629 -march=armv7-a.
10630 -mcpu=generic-arch is also permissible, and is equivalent to -march=arch -mtune=generic-arch. See -mtune
10631 for more information.
10632 -mcpu=native causes the compiler to auto-detect the CPU of the build computer. At present, this feature is
10633 only supported on GNU/Linux, and not all architectures are recognized. If the auto-detect is unsuccessful
10634 the option has no effect.
10635 -mfpu=name
10636 This specifies what floating-point hardware (or hardware emulation) is available on the target.
10637 Permissible names are: auto, vfpv2, vfpv3, vfpv3-fp16, vfpv3-d16, vfpv3-d16-fp16, vfpv3xd, vfpv3xd-fp16,
10638 neon-vfpv3, neon-fp16, vfpv4, vfpv4-d16, fpv4-sp-d16, neon-vfpv4, fpv5-d16, fpv5-sp-d16, fp-armv8,
10639 neon-fp-armv8 and crypto-neon-fp-armv8. Note that neon is an alias for neon-vfpv3 and vfp is an alias for
10640 vfpv2.
10641 The setting auto is the default and is special. It causes the compiler to select the floating-point and
10642 Advanced SIMD instructions based on the settings of -mcpu and -march.
10643 If the selected floating-point hardware includes the NEON extension (e.g. -mfpu=neon), note that floating-
10644 point operations are not generated by GCC's auto-vectorization pass unless -funsafe-math-optimizations is
10645 also specified. This is because NEON hardware does not fully implement the IEEE 754 standard for floating-
10646 point arithmetic (in particular denormal values are treated as zero), so the use of NEON instructions may
10647 lead to a loss of precision.
10648 You can also set the fpu name at function level by using the "target("fpu=")" function attributes or
10649 pragmas.
10650 -mfp16-format=name
10651 Specify the format of the "__fp16" half-precision floating-point type. Permissible names are none, ieee,
10652 and alternative; the default is none, in which case the "__fp16" type is not defined.
10653 -mstructure-size-boundary=n
10654 The sizes of all structures and unions are rounded up to a multiple of the number of bits set by this
10655 option. Permissible values are 8, 32 and 64. The default value varies for different toolchains. For the
10656 COFF targeted toolchain the default value is 8. A value of 64 is only allowed if the underlying ABI
10657 supports it.
10658 Specifying a larger number can produce faster, more efficient code, but can also increase the size of the
10659 program. Different values are potentially incompatible. Code compiled with one value cannot necessarily
10660 expect to work with code or libraries compiled with another value, if they exchange information using
10661 structures or unions.
10662 This option is deprecated.
10663 -mabort-on-noreturn
10664 Generate a call to the function "abort" at the end of a "noreturn" function. It is executed if the
10665 function tries to return.
10666 -mlong-calls
10667 -mno-long-calls
10668 Tells the compiler to perform function calls by first loading the address of the function into a register
10669 and then performing a subroutine call on this register. This switch is needed if the target function lies
10670 outside of the 64-megabyte addressing range of the offset-based version of subroutine call instruction.
10671 Even if this switch is enabled, not all function calls are turned into long calls. The heuristic is that
10672 static functions, functions that have the "short_call" attribute, functions that are inside the scope of a
10673 "#pragma no_long_calls" directive, and functions whose definitions have already been compiled within the
10674 current compilation unit are not turned into long calls. The exceptions to this rule are that weak
10675 function definitions, functions with the "long_call" attribute or the "section" attribute, and functions
10676 that are within the scope of a "#pragma long_calls" directive are always turned into long calls.
10677 This feature is not enabled by default. Specifying -mno-long-calls restores the default behavior, as does
10678 placing the function calls within the scope of a "#pragma long_calls_off" directive. Note these switches
10679 have no effect on how the compiler generates code to handle function calls via function pointers.
10680 -msingle-pic-base
10681 Treat the register used for PIC addressing as read-only, rather than loading it in the prologue for each
10682 function. The runtime system is responsible for initializing this register with an appropriate value
10683 before execution begins.
10684 -mpic-register=reg
10685 Specify the register to be used for PIC addressing. For standard PIC base case, the default is any
10686 suitable register determined by compiler. For single PIC base case, the default is R9 if target is EABI
10687 based or stack-checking is enabled, otherwise the default is R10.
10688 -mpic-data-is-text-relative
10689 Assume that the displacement between the text and data segments is fixed at static link time. This permits
10690 using PC-relative addressing operations to access data known to be in the data segment. For non-VxWorks
10691 RTP targets, this option is enabled by default. When disabled on such targets, it will enable
10692 -msingle-pic-base by default.
10693 -mpoke-function-name
10694 Write the name of each function into the text section, directly preceding the function prologue. The
10695 generated code is similar to this:
10696 t0
10697 .ascii "arm_poke_function_name", 0
10698 .align
10699 t1
10700 .word 0xff000000 (t1 - t0)
10701 arm_poke_function_name
10702 mov ip, sp
10703 stmfd sp!, {fp, ip, lr, pc}
10704 sub fp, ip, #4
10705 When performing a stack backtrace, code can inspect the value of "pc" stored at "fp 0". If the trace
10706 function then looks at location "pc - 12" and the top 8 bits are set, then we know that there is a function
10707 name embedded immediately preceding this location and has length "((pc[-3]) & 0xff000000)".
10708 -mthumb
10709 -marm
10710 Select between generating code that executes in ARM and Thumb states. The default for most configurations
10711 is to generate code that executes in ARM state, but the default can be changed by configuring GCC with the
10712 --with-mode=state configure option.
10713 You can also override the ARM and Thumb mode for each function by using the "target("thumb")" and
10714 "target("arm")" function attributes or pragmas.
10715 -mflip-thumb
10716 Switch ARM/Thumb modes on alternating functions. This option is provided for regression testing of mixed
10717 Thumb/ARM code generation, and is not intended for ordinary use in compiling code.
10718 -mtpcs-frame
10719 Generate a stack frame that is compliant with the Thumb Procedure Call Standard for all non-leaf functions.
10720 (A leaf function is one that does not call any other functions.) The default is -mno-tpcs-frame.
10721 -mtpcs-leaf-frame
10722 Generate a stack frame that is compliant with the Thumb Procedure Call Standard for all leaf functions. (A
10723 leaf function is one that does not call any other functions.) The default is -mno-apcs-leaf-frame.
10724 -mcallee-super-interworking
10725 Gives all externally visible functions in the file being compiled an ARM instruction set header which
10726 switches to Thumb mode before executing the rest of the function. This allows these functions to be called
10727 from non-interworking code. This option is not valid in AAPCS configurations because interworking is
10728 enabled by default.
10729 -mcaller-super-interworking
10730 Allows calls via function pointers (including virtual functions) to execute correctly regardless of whether
10731 the target code has been compiled for interworking or not. There is a small overhead in the cost of
10732 executing a function pointer if this option is enabled. This option is not valid in AAPCS configurations
10733 because interworking is enabled by default.
10734 -mtp=name
10735 Specify the access model for the thread local storage pointer. The valid models are soft, which generates
10736 calls to "__aeabi_read_tp", cp15, which fetches the thread pointer from "cp15" directly (supported in the
10737 arm6k architecture), and auto, which uses the best available method for the selected processor. The
10738 default setting is auto.
10739 -mtls-dialect=dialect
10740 Specify the dialect to use for accessing thread local storage. Two dialects are supported---gnu and gnu2.
10741 The gnu dialect selects the original GNU scheme for supporting local and global dynamic TLS models. The
10742 gnu2 dialect selects the GNU descriptor scheme, which provides better performance for shared libraries.
10743 The GNU descriptor scheme is compatible with the original scheme, but does require new assembler, linker
10744 and library support. Initial and local exec TLS models are unaffected by this option and always use the
10745 original scheme.
10746 -mword-relocations
10747 Only generate absolute relocations on word-sized values (i.e. R_ARM_ABS32). This is enabled by default on
10748 targets (uClinux, SymbianOS) where the runtime loader imposes this restriction, and when -fpic or -fPIC is
10749 specified. This option conflicts with -mslow-flash-data.
10750 -mfix-cortex-m3-ldrd
10751 Some Cortex-M3 cores can cause data corruption when "ldrd" instructions with overlapping destination and
10752 base registers are used. This option avoids generating these instructions. This option is enabled by
10753 default when -mcpu=cortex-m3 is specified.
10754 -munaligned-access
10755 -mno-unaligned-access
10756 Enables (or disables) reading and writing of 16- and 32- bit values from addresses that are not 16- or 32-
10757 bit aligned. By default unaligned access is disabled for all pre-ARMv6, all ARMv6-M and for ARMv8-M
10758 Baseline architectures, and enabled for all other architectures. If unaligned access is not enabled then
10759 words in packed data structures are accessed a byte at a time.
10760 The ARM attribute "Tag_CPU_unaligned_access" is set in the generated object file to either true or false,
10761 depending upon the setting of this option. If unaligned access is enabled then the preprocessor symbol
10762 "__ARM_FEATURE_UNALIGNED" is also defined.
10763 -mneon-for-64bits
10764 This option is deprecated and has no effect.
10765 -mslow-flash-data
10766 Assume loading data from flash is slower than fetching instruction. Therefore literal load is minimized
10767 for better performance. This option is only supported when compiling for ARMv7 M-profile and off by
10768 default. It conflicts with -mword-relocations.
10769 -masm-syntax-unified
10770 Assume inline assembler is using unified asm syntax. The default is currently off which implies divided
10771 syntax. This option has no impact on Thumb2. However, this may change in future releases of GCC. Divided
10772 syntax should be considered deprecated.
10773 -mrestrict-it
10774 Restricts generation of IT blocks to conform to the rules of ARMv8-A. IT blocks can only contain a single
10775 16-bit instruction from a select set of instructions. This option is on by default for ARMv8-A Thumb mode.
10776 -mprint-tune-info
10777 Print CPU tuning information as comment in assembler file. This is an option used only for regression
10778 testing of the compiler and not intended for ordinary use in compiling code. This option is disabled by
10779 default.
10780 -mverbose-cost-dump
10781 Enable verbose cost model dumping in the debug dump files. This option is provided for use in debugging
10782 the compiler.
10783 -mpure-code
10784 Do not allow constant data to be placed in code sections. Additionally, when compiling for ELF object
10785 format give all text sections the ELF processor-specific section attribute "SHF_ARM_PURECODE". This option
10786 is only available when generating non-pic code for M-profile targets.
10787 -mcmse
10788 Generate secure code as per the "ARMv8-M Security Extensions: Requirements on Development Tools Engineering
10789 Specification", which can be found on <https://developer.arm.com/documentation/ecm0359818/latest/>.
10790 -mfix-cmse-cve-2021-35465
10791 Mitigate against a potential security issue with the "VLLDM" instruction in some M-profile devices when
10792 using CMSE (CVE-2021-365465). This option is enabled by default when the option -mcpu= is used with
10793 "cortex-m33", "cortex-m35p" or "cortex-m55". The option -mno-fix-cmse-cve-2021-35465 can be used to
10794 disable the mitigation.
10795 -mfdpic
10796 -mno-fdpic
10797 Select the FDPIC ABI, which uses 64-bit function descriptors to represent pointers to functions. When the
10798 compiler is configured for "arm-*-uclinuxfdpiceabi" targets, this option is on by default and implies -fPIE
10799 if none of the PIC/PIE-related options is provided. On other targets, it only enables the FDPIC-specific
10800 code generation features, and the user should explicitly provide the PIC/PIE-related options as needed.
10801 Note that static linking is not supported because it would still involve the dynamic linker when the
10802 program self-relocates. If such behavior is acceptable, use -static and -Wl,-dynamic-linker options.
10803 The opposite -mno-fdpic option is useful (and required) to build the Linux kernel using the same
10804 ("arm-*-uclinuxfdpiceabi") toolchain as the one used to build the userland programs.
10805 AVR Options
10806 These options are defined for AVR implementations:
10807 -mmcu=mcu
10808 Specify Atmel AVR instruction set architectures (ISA) or MCU type.
10809 The default for this option is avr2.
10810 GCC supports the following AVR devices and ISAs:
10811 "avr2"
10812 "Classic" devices with up to 8 KiB of program memory. mcu = "attiny22", "attiny26", "at90s2313",
10813 "at90s2323", "at90s2333", "at90s2343", "at90s4414", "at90s4433", "at90s4434", "at90c8534", "at90s8515",
10814 "at90s8535".
10815 "avr25"
10816 "Classic" devices with up to 8 KiB of program memory and with the "MOVW" instruction. mcu =
10817 "attiny13", "attiny13a", "attiny24", "attiny24a", "attiny25", "attiny261", "attiny261a", "attiny2313",
10818 "attiny2313a", "attiny43u", "attiny44", "attiny44a", "attiny45", "attiny48", "attiny441", "attiny461",
10819 "attiny461a", "attiny4313", "attiny84", "attiny84a", "attiny85", "attiny87", "attiny88", "attiny828",
10820 "attiny841", "attiny861", "attiny861a", "ata5272", "ata6616c", "at86rf401".
10821 "avr3"
10822 "Classic" devices with 16 KiB up to 64 KiB of program memory. mcu = "at76c711", "at43usb355".
10823 "avr31"
10824 "Classic" devices with 128 KiB of program memory. mcu = "atmega103", "at43usb320".
10825 "avr35"
10826 "Classic" devices with 16 KiB up to 64 KiB of program memory and with the "MOVW" instruction. mcu =
10827 "attiny167", "attiny1634", "atmega8u2", "atmega16u2", "atmega32u2", "ata5505", "ata6617c", "ata664251",
10828 "at90usb82", "at90usb162".
10829 "avr4"
10830 "Enhanced" devices with up to 8 KiB of program memory. mcu = "atmega48", "atmega48a", "atmega48p",
10831 "atmega48pa", "atmega48pb", "atmega8", "atmega8a", "atmega8hva", "atmega88", "atmega88a", "atmega88p",
10832 "atmega88pa", "atmega88pb", "atmega8515", "atmega8535", "ata6285", "ata6286", "ata6289", "ata6612c",
10833 "at90pwm1", "at90pwm2", "at90pwm2b", "at90pwm3", "at90pwm3b", "at90pwm81".
10834 "avr5"
10835 "Enhanced" devices with 16 KiB up to 64 KiB of program memory. mcu = "atmega16", "atmega16a",
10836 "atmega16hva", "atmega16hva2", "atmega16hvb", "atmega16hvbrevb", "atmega16m1", "atmega16u4",
10837 "atmega161", "atmega162", "atmega163", "atmega164a", "atmega164p", "atmega164pa", "atmega165",
10838 "atmega165a", "atmega165p", "atmega165pa", "atmega168", "atmega168a", "atmega168p", "atmega168pa",
10839 "atmega168pb", "atmega169", "atmega169a", "atmega169p", "atmega169pa", "atmega32", "atmega32a",
10840 "atmega32c1", "atmega32hvb", "atmega32hvbrevb", "atmega32m1", "atmega32u4", "atmega32u6", "atmega323",
10841 "atmega324a", "atmega324p", "atmega324pa", "atmega325", "atmega325a", "atmega325p", "atmega325pa",
10842 "atmega328", "atmega328p", "atmega328pb", "atmega329", "atmega329a", "atmega329p", "atmega329pa",
10843 "atmega3250", "atmega3250a", "atmega3250p", "atmega3250pa", "atmega3290", "atmega3290a", "atmega3290p",
10844 "atmega3290pa", "atmega406", "atmega64", "atmega64a", "atmega64c1", "atmega64hve", "atmega64hve2",
10845 "atmega64m1", "atmega64rfr2", "atmega640", "atmega644", "atmega644a", "atmega644p", "atmega644pa",
10846 "atmega644rfr2", "atmega645", "atmega645a", "atmega645p", "atmega649", "atmega649a", "atmega649p",
10847 "atmega6450", "atmega6450a", "atmega6450p", "atmega6490", "atmega6490a", "atmega6490p", "ata5795",
10848 "ata5790", "ata5790n", "ata5791", "ata6613c", "ata6614q", "ata5782", "ata5831", "ata8210", "ata8510",
10849 "ata5702m322", "at90pwm161", "at90pwm216", "at90pwm316", "at90can32", "at90can64", "at90scr100",
10850 "at90usb646", "at90usb647", "at94k", "m3000".
10851 "avr51"
10852 "Enhanced" devices with 128 KiB of program memory. mcu = "atmega128", "atmega128a", "atmega128rfa1",
10853 "atmega128rfr2", "atmega1280", "atmega1281", "atmega1284", "atmega1284p", "atmega1284rfr2",
10854 "at90can128", "at90usb1286", "at90usb1287".
10855 "avr6"
10856 "Enhanced" devices with 3-byte PC, i.e. with more than 128 KiB of program memory. mcu =
10857 "atmega256rfr2", "atmega2560", "atmega2561", "atmega2564rfr2".
10858 "avrxmega2"
10859 "XMEGA" devices with more than 8 KiB and up to 64 KiB of program memory. mcu = "atxmega8e5",
10860 "atxmega16a4", "atxmega16a4u", "atxmega16c4", "atxmega16d4", "atxmega16e5", "atxmega32a4",
10861 "atxmega32a4u", "atxmega32c3", "atxmega32c4", "atxmega32d3", "atxmega32d4", "atxmega32e5".
10862 "avrxmega3"
10863 "XMEGA" devices with up to 64 KiB of combined program memory and RAM, and with program memory visible
10864 in the RAM address space. mcu = "attiny202", "attiny204", "attiny212", "attiny214", "attiny402",
10865 "attiny404", "attiny406", "attiny412", "attiny414", "attiny416", "attiny417", "attiny804", "attiny806",
10866 "attiny807", "attiny814", "attiny816", "attiny817", "attiny1604", "attiny1606", "attiny1607",
10867 "attiny1614", "attiny1616", "attiny1617", "attiny3214", "attiny3216", "attiny3217", "atmega808",
10868 "atmega809", "atmega1608", "atmega1609", "atmega3208", "atmega3209", "atmega4808", "atmega4809".
10869 "avrxmega4"
10870 "XMEGA" devices with more than 64 KiB and up to 128 KiB of program memory. mcu = "atxmega64a3",
10871 "atxmega64a3u", "atxmega64a4u", "atxmega64b1", "atxmega64b3", "atxmega64c3", "atxmega64d3",
10872 "atxmega64d4".
10873 "avrxmega5"
10874 "XMEGA" devices with more than 64 KiB and up to 128 KiB of program memory and more than 64 KiB of RAM.
10875 mcu = "atxmega64a1", "atxmega64a1u".
10876 "avrxmega6"
10877 "XMEGA" devices with more than 128 KiB of program memory. mcu = "atxmega128a3", "atxmega128a3u",
10878 "atxmega128b1", "atxmega128b3", "atxmega128c3", "atxmega128d3", "atxmega128d4", "atxmega192a3",
10879 "atxmega192a3u", "atxmega192c3", "atxmega192d3", "atxmega256a3", "atxmega256a3b", "atxmega256a3bu",
10880 "atxmega256a3u", "atxmega256c3", "atxmega256d3", "atxmega384c3", "atxmega384d3".
10881 "avrxmega7"
10882 "XMEGA" devices with more than 128 KiB of program memory and more than 64 KiB of RAM. mcu =
10883 "atxmega128a1", "atxmega128a1u", "atxmega128a4u".
10884 "avrtiny"
10885 "TINY" Tiny core devices with 512 B up to 4 KiB of program memory. mcu = "attiny4", "attiny5",
10886 "attiny9", "attiny10", "attiny20", "attiny40".
10887 "avr1"
10888 This ISA is implemented by the minimal AVR core and supported for assembler only. mcu = "attiny11",
10889 "attiny12", "attiny15", "attiny28", "at90s1200".
10890 -mabsdata
10891 Assume that all data in static storage can be accessed by LDS / STS instructions. This option has only an
10892 effect on reduced Tiny devices like ATtiny40. See also the "absdata" AVR Variable Attributes,variable
10893 attribute.
10894 -maccumulate-args
10895 Accumulate outgoing function arguments and acquire/release the needed stack space for outgoing function
10896 arguments once in function prologue/epilogue. Without this option, outgoing arguments are pushed before
10897 calling a function and popped afterwards.
10898 Popping the arguments after the function call can be expensive on AVR so that accumulating the stack space
10899 might lead to smaller executables because arguments need not be removed from the stack after such a
10900 function call.
10901 This option can lead to reduced code size for functions that perform several calls to functions that get
10902 their arguments on the stack like calls to printf-like functions.
10903 -mbranch-cost=cost
10904 Set the branch costs for conditional branch instructions to cost. Reasonable values for cost are small,
10905 non-negative integers. The default branch cost is 0.
10906 -mcall-prologues
10907 Functions prologues/epilogues are expanded as calls to appropriate subroutines. Code size is smaller.
10908 -mdouble=bits
10909 -mlong-double=bits
10910 Set the size (in bits) of the "double" or "long double" type, respectively. Possible values for bits are
10911 32 and 64. Whether or not a specific value for bits is allowed depends on the "--with-double=" and
10912 "--with-long-double=" configure options ("https://gcc.gnu.org/install/configure.html#avr"), and the same
10913 applies for the default values of the options.
10914 -mgas-isr-prologues
10915 Interrupt service routines (ISRs) may use the "__gcc_isr" pseudo instruction supported by GNU Binutils. If
10916 this option is on, the feature can still be disabled for individual ISRs by means of the AVR Function
10917 Attributes,,"no_gccisr" function attribute. This feature is activated per default if optimization is on
10918 (but not with -Og, @pxref{Optimize Options}), and if GNU Binutils support PR21683
10919 ("https://sourceware.org/PR21683").
10920 -mint8
10921 Assume "int" to be 8-bit integer. This affects the sizes of all types: a "char" is 1 byte, an "int" is 1
10922 byte, a "long" is 2 bytes, and "long long" is 4 bytes. Please note that this option does not conform to
10923 the C standards, but it results in smaller code size.
10924 -mmain-is-OS_task
10925 Do not save registers in "main". The effect is the same like attaching attribute AVR Function
10926 Attributes,,"OS_task" to "main". It is activated per default if optimization is on.
10927 -mn-flash=num
10928 Assume that the flash memory has a size of num times 64 KiB.
10929 -mno-interrupts
10930 Generated code is not compatible with hardware interrupts. Code size is smaller.
10931 -mrelax
10932 Try to replace "CALL" resp. "JMP" instruction by the shorter "RCALL" resp. "RJMP" instruction if
10933 applicable. Setting -mrelax just adds the --mlink-relax option to the assembler's command line and the
10934 --relax option to the linker's command line.
10935 Jump relaxing is performed by the linker because jump offsets are not known before code is located.
10936 Therefore, the assembler code generated by the compiler is the same, but the instructions in the executable
10937 may differ from instructions in the assembler code.
10938 Relaxing must be turned on if linker stubs are needed, see the section on "EIND" and linker stubs below.
10939 -mrmw
10940 Assume that the device supports the Read-Modify-Write instructions "XCH", "LAC", "LAS" and "LAT".
10941 -mshort-calls
10942 Assume that "RJMP" and "RCALL" can target the whole program memory.
10943 This option is used internally for multilib selection. It is not an optimization option, and you don't
10944 need to set it by hand.
10945 -msp8
10946 Treat the stack pointer register as an 8-bit register, i.e. assume the high byte of the stack pointer is
10947 zero. In general, you don't need to set this option by hand.
10948 This option is used internally by the compiler to select and build multilibs for architectures "avr2" and
10949 "avr25". These architectures mix devices with and without "SPH". For any setting other than -mmcu=avr2 or
10950 -mmcu=avr25 the compiler driver adds or removes this option from the compiler proper's command line,
10951 because the compiler then knows if the device or architecture has an 8-bit stack pointer and thus no "SPH"
10952 register or not.
10953 -mstrict-X
10954 Use address register "X" in a way proposed by the hardware. This means that "X" is only used in indirect,
10955 post-increment or pre-decrement addressing.
10956 Without this option, the "X" register may be used in the same way as "Y" or "Z" which then is emulated by
10957 additional instructions. For example, loading a value with "X const" addressing with a small non-negative
10958 "const < 64" to a register Rn is performed as
10959 adiw r26, const ; X = const
10960 ld <Rn>, X ; <Rn> = *X
10961 sbiw r26, const ; X -= const
10962 -mtiny-stack
10963 Only change the lower 8 bits of the stack pointer.
10964 -mfract-convert-truncate
10965 Allow to use truncation instead of rounding towards zero for fractional fixed-point types.
10966 -nodevicelib
10967 Don't link against AVR-LibC's device specific library "lib<mcu>.a".
10968 -nodevicespecs
10969 Don't add -specs=device-specs/specs-mcu to the compiler driver's command line. The user takes
10970 responsibility for supplying the sub-processes like compiler proper, assembler and linker with appropriate
10971 command line options. This means that the user has to supply her private device specs file by means of
10972 -specs=path-to-specs-file. There is no more need for option -mmcu=mcu.
10973 This option can also serve as a replacement for the older way of specifying custom device-specs files that
10974 needed -B some-path to point to a directory which contains a folder named "device-specs" which contains a
10975 specs file named "specs-mcu", where mcu was specified by -mmcu=mcu.
10976 -Waddr-space-convert
10977 Warn about conversions between address spaces in the case where the resulting address space is not
10978 contained in the incoming address space.
10979 -Wmisspelled-isr
10980 Warn if the ISR is misspelled, i.e. without __vector prefix. Enabled by default.
10981 "EIND" and Devices with More Than 128 Ki Bytes of Flash
10982 Pointers in the implementation are 16 bits wide. The address of a function or label is represented as word
10983 address so that indirect jumps and calls can target any code address in the range of 64 Ki words.
10984 In order to facilitate indirect jump on devices with more than 128 Ki bytes of program memory space, there is a
10985 special function register called "EIND" that serves as most significant part of the target address when
10986 "EICALL" or "EIJMP" instructions are used.
10987 Indirect jumps and calls on these devices are handled as follows by the compiler and are subject to some
10988 limitations:
10989 * The compiler never sets "EIND".
10990 * The compiler uses "EIND" implicitly in "EICALL"/"EIJMP" instructions or might read "EIND" directly in order
10991 to emulate an indirect call/jump by means of a "RET" instruction.
10992 * The compiler assumes that "EIND" never changes during the startup code or during the application. In
10993 particular, "EIND" is not saved/restored in function or interrupt service routine prologue/epilogue.
10994 * For indirect calls to functions and computed goto, the linker generates stubs. Stubs are jump pads
10995 sometimes also called trampolines. Thus, the indirect call/jump jumps to such a stub. The stub contains a
10996 direct jump to the desired address.
10997 * Linker relaxation must be turned on so that the linker generates the stubs correctly in all situations. See
10998 the compiler option -mrelax and the linker option --relax. There are corner cases where the linker is
10999 supposed to generate stubs but aborts without relaxation and without a helpful error message.
11000 * The default linker script is arranged for code with "EIND = 0". If code is supposed to work for a setup
11001 with "EIND != 0", a custom linker script has to be used in order to place the sections whose name start
11002 with ".trampolines" into the segment where "EIND" points to.
11003 * The startup code from libgcc never sets "EIND". Notice that startup code is a blend of code from libgcc
11004 and AVR-LibC. For the impact of AVR-LibC on "EIND", see the AVR-LibC user manual
11005 ("http://nongnu.org/avr-libc/user-manual/").
11006 * It is legitimate for user-specific startup code to set up "EIND" early, for example by means of
11007 initialization code located in section ".init3". Such code runs prior to general startup code that
11008 initializes RAM and calls constructors, but after the bit of startup code from AVR-LibC that sets "EIND" to
11009 the segment where the vector table is located.
11010 #include <avr/io.h>
11011 static void
11012 __attribute__((section(".init3"),naked,used,no_instrument_function))
11013 init3_set_eind (void)
11014 {
11015 __asm volatile ("ldi r24,pm_hh8(__trampolines_start)\n\t"
11016 "out %i0,r24" :: "n" (&EIND) : "r24","memory");
11017 }
11018 The "__trampolines_start" symbol is defined in the linker script.
11019 * Stubs are generated automatically by the linker if the following two conditions are met:
11020 -<The address of a label is taken by means of the "gs" modifier>
11021 (short for generate stubs) like so:
11022 LDI r24, lo8(gs(<func>))
11023 LDI r25, hi8(gs(<func>))
11024 -<The final location of that label is in a code segment>
11025 outside the segment where the stubs are located.
11026 * The compiler emits such "gs" modifiers for code labels in the following situations:
11027 -<Taking address of a function or code label.>
11028 -<Computed goto.>
11029 -<If prologue-save function is used, see -mcall-prologues>
11030 command-line option.
11031 -<Switch/case dispatch tables. If you do not want such dispatch>
11032 tables you can specify the -fno-jump-tables command-line option.
11033 -<C and C constructors/destructors called during startup/shutdown.>
11034 -<If the tools hit a "gs()" modifier explained above.>
11035 * Jumping to non-symbolic addresses like so is not supported:
11036 int main (void)
11037 {
11038 /* Call function at word address 0x2 */
11039 return ((int(*)(void)) 0x2)();
11040 }
11041 Instead, a stub has to be set up, i.e. the function has to be called through a symbol ("func_4" in the
11042 example):
11043 int main (void)
11044 {
11045 extern int func_4 (void);
11046 /* Call function at byte address 0x4 */
11047 return func_4();
11048 }
11049 and the application be linked with -Wl,--defsym,func_4=0x4. Alternatively, "func_4" can be defined in the
11050 linker script.
11051 Handling of the "RAMPD", "RAMPX", "RAMPY" and "RAMPZ" Special Function Registers
11052 Some AVR devices support memories larger than the 64 KiB range that can be accessed with 16-bit pointers. To
11053 access memory locations outside this 64 KiB range, the content of a "RAMP" register is used as high part of the
11054 address: The "X", "Y", "Z" address register is concatenated with the "RAMPX", "RAMPY", "RAMPZ" special function
11055 register, respectively, to get a wide address. Similarly, "RAMPD" is used together with direct addressing.
11056 * The startup code initializes the "RAMP" special function registers with zero.
11057 * If a AVR Named Address Spaces,named address space other than generic or "__flash" is used, then "RAMPZ" is
11058 set as needed before the operation.
11059 * If the device supports RAM larger than 64 KiB and the compiler needs to change "RAMPZ" to accomplish an
11060 operation, "RAMPZ" is reset to zero after the operation.
11061 * If the device comes with a specific "RAMP" register, the ISR prologue/epilogue saves/restores that SFR and
11062 initializes it with zero in case the ISR code might (implicitly) use it.
11063 * RAM larger than 64 KiB is not supported by GCC for AVR targets. If you use inline assembler to read from
11064 locations outside the 16-bit address range and change one of the "RAMP" registers, you must reset it to
11065 zero after the access.
11066 AVR Built-in Macros
11067 GCC defines several built-in macros so that the user code can test for the presence or absence of features.
11068 Almost any of the following built-in macros are deduced from device capabilities and thus triggered by the
11069 -mmcu= command-line option.
11070 For even more AVR-specific built-in macros see AVR Named Address Spaces and AVR Built-in Functions.
11071 "__AVR_ARCH__"
11072 Build-in macro that resolves to a decimal number that identifies the architecture and depends on the
11073 -mmcu=mcu option. Possible values are:
11074 2, 25, 3, 31, 35, 4, 5, 51, 6
11075 for mcu="avr2", "avr25", "avr3", "avr31", "avr35", "avr4", "avr5", "avr51", "avr6",
11076 respectively and
11077 100, 102, 103, 104, 105, 106, 107
11078 for mcu="avrtiny", "avrxmega2", "avrxmega3", "avrxmega4", "avrxmega5", "avrxmega6", "avrxmega7",
11079 respectively. If mcu specifies a device, this built-in macro is set accordingly. For example, with
11080 -mmcu=atmega8 the macro is defined to 4.
11081 "__AVR_Device__"
11082 Setting -mmcu=device defines this built-in macro which reflects the device's name. For example,
11083 -mmcu=atmega8 defines the built-in macro "__AVR_ATmega8__", -mmcu=attiny261a defines "__AVR_ATtiny261A__",
11084 etc.
11085 The built-in macros' names follow the scheme "__AVR_Device__" where Device is the device name as from the
11086 AVR user manual. The difference between Device in the built-in macro and device in -mmcu=device is that the
11087 latter is always lowercase.
11088 If device is not a device but only a core architecture like avr51, this macro is not defined.
11089 "__AVR_DEVICE_NAME__"
11090 Setting -mmcu=device defines this built-in macro to the device's name. For example, with -mmcu=atmega8 the
11091 macro is defined to "atmega8".
11092 If device is not a device but only a core architecture like avr51, this macro is not defined.
11093 "__AVR_XMEGA__"
11094 The device / architecture belongs to the XMEGA family of devices.
11095 "__AVR_HAVE_ELPM__"
11096 The device has the "ELPM" instruction.
11097 "__AVR_HAVE_ELPMX__"
11098 The device has the "ELPM Rn,Z" and "ELPM Rn,Z " instructions.
11099 "__AVR_HAVE_MOVW__"
11100 The device has the "MOVW" instruction to perform 16-bit register-register moves.
11101 "__AVR_HAVE_LPMX__"
11102 The device has the "LPM Rn,Z" and "LPM Rn,Z " instructions.
11103 "__AVR_HAVE_MUL__"
11104 The device has a hardware multiplier.
11105 "__AVR_HAVE_JMP_CALL__"
11106 The device has the "JMP" and "CALL" instructions. This is the case for devices with more than 8 KiB of
11107 program memory.
11108 "__AVR_HAVE_EIJMP_EICALL__"
11109 "__AVR_3_BYTE_PC__"
11110 The device has the "EIJMP" and "EICALL" instructions. This is the case for devices with more than 128 KiB
11111 of program memory. This also means that the program counter (PC) is 3 bytes wide.
11112 "__AVR_2_BYTE_PC__"
11113 The program counter (PC) is 2 bytes wide. This is the case for devices with up to 128 KiB of program
11114 memory.
11115 "__AVR_HAVE_8BIT_SP__"
11116 "__AVR_HAVE_16BIT_SP__"
11117 The stack pointer (SP) register is treated as 8-bit respectively 16-bit register by the compiler. The
11118 definition of these macros is affected by -mtiny-stack.
11119 "__AVR_HAVE_SPH__"
11120 "__AVR_SP8__"
11121 The device has the SPH (high part of stack pointer) special function register or has an 8-bit stack
11122 pointer, respectively. The definition of these macros is affected by -mmcu= and in the cases of -mmcu=avr2
11123 and -mmcu=avr25 also by -msp8.
11124 "__AVR_HAVE_RAMPD__"
11125 "__AVR_HAVE_RAMPX__"
11126 "__AVR_HAVE_RAMPY__"
11127 "__AVR_HAVE_RAMPZ__"
11128 The device has the "RAMPD", "RAMPX", "RAMPY", "RAMPZ" special function register, respectively.
11129 "__NO_INTERRUPTS__"
11130 This macro reflects the -mno-interrupts command-line option.
11131 "__AVR_ERRATA_SKIP__"
11132 "__AVR_ERRATA_SKIP_JMP_CALL__"
11133 Some AVR devices (AT90S8515, ATmega103) must not skip 32-bit instructions because of a hardware erratum.
11134 Skip instructions are "SBRS", "SBRC", "SBIS", "SBIC" and "CPSE". The second macro is only defined if
11135 "__AVR_HAVE_JMP_CALL__" is also set.
11136 "__AVR_ISA_RMW__"
11137 The device has Read-Modify-Write instructions (XCH, LAC, LAS and LAT).
11138 "__AVR_SFR_OFFSET__=offset"
11139 Instructions that can address I/O special function registers directly like "IN", "OUT", "SBI", etc. may use
11140 a different address as if addressed by an instruction to access RAM like "LD" or "STS". This offset depends
11141 on the device architecture and has to be subtracted from the RAM address in order to get the respective I/O
11142 address.
11143 "__AVR_SHORT_CALLS__"
11144 The -mshort-calls command line option is set.
11145 "__AVR_PM_BASE_ADDRESS__=addr"
11146 Some devices support reading from flash memory by means of "LD*" instructions. The flash memory is seen in
11147 the data address space at an offset of "__AVR_PM_BASE_ADDRESS__". If this macro is not defined, this
11148 feature is not available. If defined, the address space is linear and there is no need to put ".rodata"
11149 into RAM. This is handled by the default linker description file, and is currently available for "avrtiny"
11150 and "avrxmega3". Even more convenient, there is no need to use address spaces like "__flash" or features
11151 like attribute "progmem" and "pgm_read_*".
11152 "__WITH_AVRLIBC__"
11153 The compiler is configured to be used together with AVR-Libc. See the --with-avrlibc configure option.
11154 "__HAVE_DOUBLE_MULTILIB__"
11155 Defined if -mdouble= acts as a multilib option.
11156 "__HAVE_DOUBLE32__"
11157 "__HAVE_DOUBLE64__"
11158 Defined if the compiler supports 32-bit double resp. 64-bit double. The actual layout is specified by
11159 option -mdouble=.
11160 "__DEFAULT_DOUBLE__"
11161 The size in bits of "double" if -mdouble= is not set. To test the layout of "double" in a program, use the
11162 built-in macro "__SIZEOF_DOUBLE__".
11163 "__HAVE_LONG_DOUBLE32__"
11164 "__HAVE_LONG_DOUBLE64__"
11165 "__HAVE_LONG_DOUBLE_MULTILIB__"
11166 "__DEFAULT_LONG_DOUBLE__"
11167 Same as above, but for "long double" instead of "double".
11168 "__WITH_DOUBLE_COMPARISON__"
11169 Reflects the "--with-double-comparison={tristate|bool|libf7}" configure option
11170 ("https://gcc.gnu.org/install/configure.html#avr") and is defined to 2 or 3.
11171 "__WITH_LIBF7_LIBGCC__"
11172 "__WITH_LIBF7_MATH__"
11173 "__WITH_LIBF7_MATH_SYMBOLS__"
11174 Reflects the "--with-libf7={libgcc|math|math-symbols}" configure option
11175 ("https://gcc.gnu.org/install/configure.html#avr").
11176 Blackfin Options
11177 -mcpu=cpu[-sirevision]
11178 Specifies the name of the target Blackfin processor. Currently, cpu can be one of bf512, bf514, bf516,
11179 bf518, bf522, bf523, bf524, bf525, bf526, bf527, bf531, bf532, bf533, bf534, bf536, bf537, bf538, bf539,
11180 bf542, bf544, bf547, bf548, bf549, bf542m, bf544m, bf547m, bf548m, bf549m, bf561, bf592.
11181 The optional sirevision specifies the silicon revision of the target Blackfin processor. Any workarounds
11182 available for the targeted silicon revision are enabled. If sirevision is none, no workarounds are
11183 enabled. If sirevision is any, all workarounds for the targeted processor are enabled. The
11184 "__SILICON_REVISION__" macro is defined to two hexadecimal digits representing the major and minor numbers
11185 in the silicon revision. If sirevision is none, the "__SILICON_REVISION__" is not defined. If sirevision
11186 is any, the "__SILICON_REVISION__" is defined to be 0xffff. If this optional sirevision is not used, GCC
11187 assumes the latest known silicon revision of the targeted Blackfin processor.
11188 GCC defines a preprocessor macro for the specified cpu. For the bfin-elf toolchain, this option causes the
11189 hardware BSP provided by libgloss to be linked in if -msim is not given.
11190 Without this option, bf532 is used as the processor by default.
11191 Note that support for bf561 is incomplete. For bf561, only the preprocessor macro is defined.
11192 -msim
11193 Specifies that the program will be run on the simulator. This causes the simulator BSP provided by
11194 libgloss to be linked in. This option has effect only for bfin-elf toolchain. Certain other options, such
11195 as -mid-shared-library and -mfdpic, imply -msim.
11196 -momit-leaf-frame-pointer
11197 Don't keep the frame pointer in a register for leaf functions. This avoids the instructions to save, set
11198 up and restore frame pointers and makes an extra register available in leaf functions.
11199 -mspecld-anomaly
11200 When enabled, the compiler ensures that the generated code does not contain speculative loads after jump
11201 instructions. If this option is used, "__WORKAROUND_SPECULATIVE_LOADS" is defined.
11202 -mno-specld-anomaly
11203 Don't generate extra code to prevent speculative loads from occurring.
11204 -mcsync-anomaly
11205 When enabled, the compiler ensures that the generated code does not contain CSYNC or SSYNC instructions too
11206 soon after conditional branches. If this option is used, "__WORKAROUND_SPECULATIVE_SYNCS" is defined.
11207 -mno-csync-anomaly
11208 Don't generate extra code to prevent CSYNC or SSYNC instructions from occurring too soon after a
11209 conditional branch.
11210 -mlow64k
11211 When enabled, the compiler is free to take advantage of the knowledge that the entire program fits into the
11212 low 64k of memory.
11213 -mno-low64k
11214 Assume that the program is arbitrarily large. This is the default.
11215 -mstack-check-l1
11216 Do stack checking using information placed into L1 scratchpad memory by the uClinux kernel.
11217 -mid-shared-library
11218 Generate code that supports shared libraries via the library ID method. This allows for execute in place
11219 and shared libraries in an environment without virtual memory management. This option implies -fPIC. With
11220 a bfin-elf target, this option implies -msim.
11221 -mno-id-shared-library
11222 Generate code that doesn't assume ID-based shared libraries are being used. This is the default.
11223 -mleaf-id-shared-library
11224 Generate code that supports shared libraries via the library ID method, but assumes that this library or
11225 executable won't link against any other ID shared libraries. That allows the compiler to use faster code
11226 for jumps and calls.
11227 -mno-leaf-id-shared-library
11228 Do not assume that the code being compiled won't link against any ID shared libraries. Slower code is
11229 generated for jump and call insns.
11230 -mshared-library-id=n
11231 Specifies the identification number of the ID-based shared library being compiled. Specifying a value of 0
11232 generates more compact code; specifying other values forces the allocation of that number to the current
11233 library but is no more space- or time-efficient than omitting this option.
11234 -msep-data
11235 Generate code that allows the data segment to be located in a different area of memory from the text
11236 segment. This allows for execute in place in an environment without virtual memory management by
11237 eliminating relocations against the text section.
11238 -mno-sep-data
11239 Generate code that assumes that the data segment follows the text segment. This is the default.
11240 -mlong-calls
11241 -mno-long-calls
11242 Tells the compiler to perform function calls by first loading the address of the function into a register
11243 and then performing a subroutine call on this register. This switch is needed if the target function lies
11244 outside of the 24-bit addressing range of the offset-based version of subroutine call instruction.
11245 This feature is not enabled by default. Specifying -mno-long-calls restores the default behavior. Note
11246 these switches have no effect on how the compiler generates code to handle function calls via function
11247 pointers.
11248 -mfast-fp
11249 Link with the fast floating-point library. This library relaxes some of the IEEE floating-point standard's
11250 rules for checking inputs against Not-a-Number (NAN), in the interest of performance.
11251 -minline-plt
11252 Enable inlining of PLT entries in function calls to functions that are not known to bind locally. It has
11253 no effect without -mfdpic.
11254 -mmulticore
11255 Build a standalone application for multicore Blackfin processors. This option causes proper start files
11256 and link scripts supporting multicore to be used, and defines the macro "__BFIN_MULTICORE". It can only be
11257 used with -mcpu=bf561[-sirevision].
11258 This option can be used with -mcorea or -mcoreb, which selects the one-application-per-core programming
11259 model. Without -mcorea or -mcoreb, the single-application/dual-core programming model is used. In this
11260 model, the main function of Core B should be named as "coreb_main".
11261 If this option is not used, the single-core application programming model is used.
11262 -mcorea
11263 Build a standalone application for Core A of BF561 when using the one-application-per-core programming
11264 model. Proper start files and link scripts are used to support Core A, and the macro "__BFIN_COREA" is
11265 defined. This option can only be used in conjunction with -mmulticore.
11266 -mcoreb
11267 Build a standalone application for Core B of BF561 when using the one-application-per-core programming
11268 model. Proper start files and link scripts are used to support Core B, and the macro "__BFIN_COREB" is
11269 defined. When this option is used, "coreb_main" should be used instead of "main". This option can only be
11270 used in conjunction with -mmulticore.
11271 -msdram
11272 Build a standalone application for SDRAM. Proper start files and link scripts are used to put the
11273 application into SDRAM, and the macro "__BFIN_SDRAM" is defined. The loader should initialize SDRAM before
11274 loading the application.
11275 -micplb
11276 Assume that ICPLBs are enabled at run time. This has an effect on certain anomaly workarounds. For Linux
11277 targets, the default is to assume ICPLBs are enabled; for standalone applications the default is off.
11278 C6X Options
11279 -march=name
11280 This specifies the name of the target architecture. GCC uses this name to determine what kind of
11281 instructions it can emit when generating assembly code. Permissible names are: c62x, c64x, c64x , c67x,
11282 c67x , c674x.
11283 -mbig-endian
11284 Generate code for a big-endian target.
11285 -mlittle-endian
11286 Generate code for a little-endian target. This is the default.
11287 -msim
11288 Choose startup files and linker script suitable for the simulator.
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